# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s

--- |
  define dso_local arm_aapcs_vfpcc void @multi_cond_iter_count(i32* nocapture %0, i32* nocapture readonly %1, i32 %2, i32 %3) local_unnamed_addr #0 {
    %5 = icmp eq i32 %3, 2
    %6 = select i1 %5, i32 2, i32 4
    %7 = icmp eq i32 %3, 4
    %8 = select i1 %7, i32 1, i32 %6
    %9 = shl i32 %2, %8
    %10 = icmp eq i32 %9, 0
    br i1 %10, label %64, label %11

  11:                                               ; preds = %4
    %12 = getelementptr i32, i32* %0, i32 %9
    %13 = getelementptr i32, i32* %1, i32 %9
    %14 = icmp ugt i32* %13, %0
    %15 = icmp ugt i32* %12, %1
    %16 = and i1 %14, %15
    %17 = add i32 %9, 3
    %18 = lshr i32 %17, 2
    %19 = shl nuw i32 %18, 2
    %20 = add i32 %19, -4
    %21 = lshr i32 %20, 2
    %22 = add nuw nsw i32 %21, 1
    br i1 %16, label %23, label %32

  23:                                               ; preds = %11
    %24 = add i32 %9, -1
    %25 = and i32 %9, 2
    %26 = icmp ult i32 %24, 3
    %27 = add i32 %9, -4
    %28 = sub i32 %27, %25
    %29 = lshr i32 %28, 2
    %30 = add nuw nsw i32 %29, 1
    br i1 %26, label %49, label %31

  31:                                               ; preds = %23
    %start1 = call i32 @llvm.start.loop.iterations.i32(i32 %30)
    br label %65

  32:                                               ; preds = %11
    %start2 = call i32 @llvm.start.loop.iterations.i32(i32 %22)
    br label %33

  33:                                               ; preds = %33, %32
    %34 = phi i32* [ %46, %33 ], [ %0, %32 ]
    %35 = phi i32* [ %45, %33 ], [ %1, %32 ]
    %36 = phi i32 [ %start2, %32 ], [ %47, %33 ]
    %37 = phi i32 [ %9, %32 ], [ %41, %33 ]
    %38 = bitcast i32* %34 to <4 x i32>*
    %39 = bitcast i32* %35 to <4 x i32>*
    %40 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %37)
    %41 = sub i32 %37, 4
    %42 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %39, i32 4, <4 x i1> %40, <4 x i32> undef)
    %43 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %38, i32 4, <4 x i1> %40, <4 x i32> undef)
    %44 = mul nsw <4 x i32> %43, %42
    call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %44, <4 x i32>* %38, i32 4, <4 x i1> %40)
    %45 = getelementptr i32, i32* %35, i32 4
    %46 = getelementptr i32, i32* %34, i32 4
    %47 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %36, i32 1)
    %48 = icmp ne i32 %47, 0
    br i1 %48, label %33, label %64

  49:                                               ; preds = %65, %23
    %50 = phi i32 [ 0, %23 ], [ %107, %65 ]
    %51 = icmp eq i32 %25, 0
    br i1 %51, label %64, label %52

  52:                                               ; preds = %49
    %53 = getelementptr inbounds i32, i32* %1, i32 %50
    %54 = load i32, i32* %53, align 4
    %55 = getelementptr inbounds i32, i32* %0, i32 %50
    %56 = load i32, i32* %55, align 4
    %57 = mul nsw i32 %56, %54
    store i32 %57, i32* %55, align 4
    %58 = add nuw i32 %50, 1
    %59 = getelementptr inbounds i32, i32* %1, i32 %58
    %60 = load i32, i32* %59, align 4
    %61 = getelementptr inbounds i32, i32* %0, i32 %58
    %62 = load i32, i32* %61, align 4
    %63 = mul nsw i32 %62, %60
    store i32 %63, i32* %61, align 4
    br label %64

  64:                                               ; preds = %33, %52, %49, %4
    ret void

  65:                                               ; preds = %65, %31
    %66 = phi i32 [ %108, %65 ], [ 0, %31 ]
    %67 = phi i32 [ 0, %31 ], [ %107, %65 ]
    %68 = phi i32 [ %start1, %31 ], [ %109, %65 ]
    %69 = bitcast i32* %0 to i8*
    %70 = bitcast i32* %1 to i8*
    %71 = getelementptr i8, i8* %70, i32 %66
    %72 = bitcast i8* %71 to i32*
    %73 = bitcast i32* %72 to i32*
    %74 = load i32, i32* %73, align 4
    %75 = getelementptr i8, i8* %69, i32 %66
    %76 = bitcast i8* %75 to i32*
    %77 = bitcast i32* %76 to i32*
    %78 = load i32, i32* %77, align 4
    %79 = mul nsw i32 %78, %74
    store i32 %79, i32* %77, align 4
    %80 = getelementptr i8, i8* %70, i32 %66
    %81 = bitcast i8* %80 to i32*
    %82 = getelementptr i32, i32* %81, i32 1
    %83 = load i32, i32* %82, align 4
    %84 = getelementptr i8, i8* %69, i32 %66
    %85 = bitcast i8* %84 to i32*
    %86 = getelementptr i32, i32* %85, i32 1
    %87 = load i32, i32* %86, align 4
    %88 = mul nsw i32 %87, %83
    store i32 %88, i32* %86, align 4
    %89 = getelementptr i8, i8* %70, i32 %66
    %90 = bitcast i8* %89 to i32*
    %91 = getelementptr i32, i32* %90, i32 2
    %92 = load i32, i32* %91, align 4
    %93 = getelementptr i8, i8* %69, i32 %66
    %94 = bitcast i8* %93 to i32*
    %95 = getelementptr i32, i32* %94, i32 2
    %96 = load i32, i32* %95, align 4
    %97 = mul nsw i32 %96, %92
    store i32 %97, i32* %95, align 4
    %98 = getelementptr i8, i8* %70, i32 %66
    %99 = bitcast i8* %98 to i32*
    %100 = getelementptr i32, i32* %99, i32 3
    %101 = load i32, i32* %100, align 4
    %102 = getelementptr i8, i8* %69, i32 %66
    %103 = bitcast i8* %102 to i32*
    %104 = getelementptr i32, i32* %103, i32 3
    %105 = load i32, i32* %104, align 4
    %106 = mul nsw i32 %105, %101
    store i32 %106, i32* %104, align 4
    %107 = add nuw i32 %67, 4
    %108 = add i32 %66, 16
    %109 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %68, i32 1)
    %110 = icmp ne i32 %109, 0
    br i1 %110, label %65, label %49
  }

  declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) #1
  declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) #2
  declare i32 @llvm.start.loop.iterations.i32(i32) #3
  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3
  declare <4 x i1> @llvm.arm.mve.vctp32(i32) #4

...
---
name:            multi_cond_iter_count
alignment:       2
tracksRegLiveness: true
registers:       []
liveins:
  - { reg: '$r0', virtual-reg: '' }
  - { reg: '$r1', virtual-reg: '' }
  - { reg: '$r2', virtual-reg: '' }
  - { reg: '$r3', virtual-reg: '' }
frameInfo:
  stackSize:       32
  offsetAdjustment: -24
  maxAlignment:    4
fixedStack:      []
stack:
  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 4, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 5, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r10', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 6, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r9', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 7, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:       []
constants:       []
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: multi_cond_iter_count
  ; CHECK: bb.0 (%ir-block.4):
  ; CHECK:   successors: %bb.4(0x30000000), %bb.1(0x50000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r10
  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 20
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r6, -12
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r5, -16
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r4, -20
  ; CHECK:   dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa $r7, 8
  ; CHECK:   $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r8, killed $r9, killed $r10
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r10, -24
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r9, -28
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r8, -32
  ; CHECK:   tCMPi8 renamable $r3, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   $r12 = tMOVr $r3, 14 /* CC::al */, $noreg
  ; CHECK:   t2IT 1, 8, implicit-def $itstate
  ; CHECK:   $r12 = t2MOVi 4, 1 /* CC::ne */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
  ; CHECK:   tCMPi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   t2IT 0, 8, implicit-def $itstate
  ; CHECK:   $r12 = t2MOVi 1, 0 /* CC::eq */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
  ; CHECK:   renamable $r3 = t2LSLrr killed renamable $r2, killed renamable $r12, 14 /* CC::al */, $noreg, def $cpsr
  ; CHECK:   tBcc %bb.4, 0 /* CC::eq */, killed $cpsr
  ; CHECK: bb.1 (%ir-block.11):
  ; CHECK:   successors: %bb.2(0x55555555), %bb.5(0x2aaaaaab)
  ; CHECK:   liveins: $r0, $r1, $r3
  ; CHECK:   renamable $r2 = t2ADDrs renamable $r1, renamable $r3, 18, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   tCMPr killed renamable $r2, renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   t2IT 8, 4, implicit-def $itstate
  ; CHECK:   renamable $r2 = t2ADDrs renamable $r0, renamable $r3, 18, 8 /* CC::hi */, $cpsr, $noreg, implicit $itstate
  ; CHECK:   tCMPr killed renamable $r2, renamable $r1, 8 /* CC::hi */, killed $cpsr, implicit-def $cpsr, implicit killed $itstate
  ; CHECK:   tBcc %bb.5, 8 /* CC::hi */, killed $cpsr
  ; CHECK: bb.2 (%ir-block.32):
  ; CHECK:   successors: %bb.3(0x80000000)
  ; CHECK:   liveins: $r0, $r1, $r3
  ; CHECK:   $r2 = tMOVr $r0, 14 /* CC::al */, $noreg
  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r3
  ; CHECK: bb.3 (%ir-block.33):
  ; CHECK:   successors: %bb.3(0x7c000000), %bb.4(0x04000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2
  ; CHECK:   renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg
  ; CHECK:   renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg
  ; CHECK:   renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
  ; CHECK:   MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg, $noreg
  ; CHECK:   $r0 = tMOVr $r2, 14 /* CC::al */, $noreg
  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.3
  ; CHECK: bb.4 (%ir-block.64):
  ; CHECK:   $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10
  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
  ; CHECK: bb.5 (%ir-block.23):
  ; CHECK:   successors: %bb.6(0x40000000), %bb.7(0x40000000)
  ; CHECK:   liveins: $r0, $r1, $r3
  ; CHECK:   renamable $r2, dead $cpsr = tSUBi3 renamable $r3, 1, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r12 = t2ANDri renamable $r3, 2, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   tCMPi8 killed renamable $r2, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   tBcc %bb.7, 2 /* CC::hs */, killed $cpsr
  ; CHECK: bb.6:
  ; CHECK:   successors: %bb.9(0x80000000)
  ; CHECK:   liveins: $r0, $r1, $r12
  ; CHECK:   renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
  ; CHECK:   tB %bb.9, 14 /* CC::al */, $noreg
  ; CHECK: bb.7 (%ir-block.31):
  ; CHECK:   successors: %bb.8(0x80000000)
  ; CHECK:   liveins: $r0, $r1, $r3, $r12
  ; CHECK:   renamable $r2 = t2BICri killed renamable $r3, 2, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
  ; CHECK: bb.8 (%ir-block.65):
  ; CHECK:   successors: %bb.8(0x7c000000), %bb.9(0x04000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r12
  ; CHECK:   renamable $r4 = tLDRr renamable $r1, $r2, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r5 = tLDRr renamable $r0, $r2, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r4, dead $cpsr = nsw tMUL killed renamable $r5, killed renamable $r4, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r5, dead $cpsr = tADDrr renamable $r0, renamable $r2, 14 /* CC::al */, $noreg
  ; CHECK:   $r10, $r8 = t2LDRDi8 $r5, 4, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r9 = t2LDRi12 renamable $r5, 12, 14 /* CC::al */, $noreg
  ; CHECK:   tSTRr killed renamable $r4, renamable $r0, $r2, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r2, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r6 = tLDRi renamable $r4, 1, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r6 = nsw t2MUL killed renamable $r10, killed renamable $r6, 14 /* CC::al */, $noreg
  ; CHECK:   tSTRi killed renamable $r6, renamable $r5, 1, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r6 = tLDRi renamable $r4, 2, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r6 = nsw t2MUL killed renamable $r8, killed renamable $r6, 14 /* CC::al */, $noreg
  ; CHECK:   tSTRi killed renamable $r6, renamable $r5, 2, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r4 = tLDRi killed renamable $r4, 3, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r4 = nsw t2MUL killed renamable $r9, killed renamable $r4, 14 /* CC::al */, $noreg
  ; CHECK:   tSTRi killed renamable $r4, killed renamable $r5, 3, 14 /* CC::al */, $noreg
  ; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.8
  ; CHECK: bb.9 (%ir-block.49):
  ; CHECK:   successors: %bb.4(0x40000000), %bb.10(0x40000000)
  ; CHECK:   liveins: $r0, $r1, $r3, $r12
  ; CHECK:   t2CMPri killed renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   tBcc %bb.4, 0 /* CC::eq */, killed $cpsr
  ; CHECK: bb.10 (%ir-block.52):
  ; CHECK:   liveins: $r0, $r1, $r3
  ; CHECK:   renamable $r12 = t2LDRs renamable $r1, renamable $r3, 2, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r12 = nsw t2MUL killed renamable $r2, killed renamable $r12, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r2, dead $cpsr = tADDi3 renamable $r3, 1, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $lr = t2LDRs renamable $r0, renamable $r2, 2, 14 /* CC::al */, $noreg
  ; CHECK:   t2STRs killed renamable $r12, renamable $r0, killed renamable $r3, 2, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r1 = t2LDRs killed renamable $r1, renamable $r2, 2, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r1 = nsw t2MUL killed renamable $lr, killed renamable $r1, 14 /* CC::al */, $noreg
  ; CHECK:   t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r2, 2, 14 /* CC::al */, $noreg
  ; CHECK:   $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10
  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
  bb.0 (%ir-block.4):
    successors: %bb.4(0x30000000), %bb.1(0x50000000)
    liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r10

    frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
    frame-setup CFI_INSTRUCTION def_cfa_offset 20
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r7, -8
    frame-setup CFI_INSTRUCTION offset $r6, -12
    frame-setup CFI_INSTRUCTION offset $r5, -16
    frame-setup CFI_INSTRUCTION offset $r4, -20
    $r7 = frame-setup tADDrSPi $sp, 3, 14, $noreg
    frame-setup CFI_INSTRUCTION def_cfa $r7, 8
    $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r8, killed $r9, killed $r10
    frame-setup CFI_INSTRUCTION offset $r10, -24
    frame-setup CFI_INSTRUCTION offset $r9, -28
    frame-setup CFI_INSTRUCTION offset $r8, -32
    tCMPi8 renamable $r3, 2, 14, $noreg, implicit-def $cpsr
    $r12 = tMOVr $r3, 14, $noreg
    t2IT 1, 8, implicit-def $itstate
    $r12 = t2MOVi 4, 1, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
    tCMPi8 killed renamable $r3, 4, 14, $noreg, implicit-def $cpsr
    t2IT 0, 8, implicit-def $itstate
    $r12 = t2MOVi 1, 0, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
    renamable $r3 = t2LSLrr killed renamable $r2, killed renamable $r12, 14, $noreg, def $cpsr
    tBcc %bb.4, 0, killed $cpsr

  bb.1 (%ir-block.11):
    successors: %bb.2(0x80000000), %bb.5(0x40000000)
    liveins: $r0, $r1, $r3

    renamable $r2 = t2ADDrs renamable $r1, renamable $r3, 18, 14, $noreg, $noreg
    tCMPr killed renamable $r2, renamable $r0, 14, $noreg, implicit-def $cpsr
    t2IT 8, 4, implicit-def $itstate
    renamable $r2 = t2ADDrs renamable $r0, renamable $r3, 18, 8, $cpsr, $noreg, implicit $itstate
    tCMPr killed renamable $r2, renamable $r1, 8, killed $cpsr, implicit-def $cpsr, implicit killed $itstate
    tBcc %bb.5, 8, killed $cpsr

  bb.2 (%ir-block.32):
    successors: %bb.3(0x80000000)
    liveins: $r0, $r1, $r3

    renamable $r2, dead $cpsr = tADDi3 renamable $r3, 3, 14, $noreg
    renamable $r2 = t2BICri killed renamable $r2, 3, 14, $noreg, $noreg
    renamable $r12 = t2SUBri killed renamable $r2, 4, 14, $noreg, $noreg
    renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg
    renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg
    $r2 = tMOVr $r0, 14, $noreg
    $lr = t2DoLoopStart renamable $lr

  bb.3 (%ir-block.33):
    successors: %bb.3(0x7c000000), %bb.4(0x04000000)
    liveins: $lr, $r0, $r1, $r2, $r3

    renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
    MVE_VPST 4, implicit $vpr
    renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg
    renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr, $noreg
    renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
    renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
    MVE_VPST 8, implicit $vpr
    MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg
    renamable $lr = t2LoopDec killed renamable $lr, 1
    $r0 = tMOVr $r2, 14, $noreg
    t2LoopEnd renamable $lr, %bb.3, implicit-def dead $cpsr
    tB %bb.4, 14, $noreg

  bb.4 (%ir-block.64):
    $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r8, def $r9, def $r10
    tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc

  bb.5 (%ir-block.23):
    successors: %bb.6(0x40000000), %bb.7(0x40000000)
    liveins: $r0, $r1, $r3

    renamable $r2, dead $cpsr = tSUBi3 renamable $r3, 1, 14, $noreg
    renamable $r12 = t2ANDri renamable $r3, 2, 14, $noreg, $noreg
    tCMPi8 killed renamable $r2, 3, 14, $noreg, implicit-def $cpsr
    tBcc %bb.7, 2, killed $cpsr

  bb.6:
    successors: %bb.9(0x80000000)
    liveins: $r0, $r1, $r12

    renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg
    tB %bb.9, 14, $noreg

  bb.7 (%ir-block.31):
    successors: %bb.8(0x80000000)
    liveins: $r0, $r1, $r3, $r12

    renamable $r2 = t2BICri killed renamable $r3, 2, 14, $noreg, $noreg
    renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg
    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
    renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14, $noreg, $noreg
    renamable $r2, dead $cpsr = tMOVi8 0, 14, $noreg
    renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg
    $lr = t2DoLoopStart renamable $lr

  bb.8 (%ir-block.65):
    successors: %bb.8(0x7c000000), %bb.9(0x04000000)
    liveins: $lr, $r0, $r1, $r2, $r3, $r12

    renamable $r4 = tLDRr renamable $r1, $r2, 14, $noreg
    renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 4, 14, $noreg
    renamable $r5 = tLDRr renamable $r0, $r2, 14, $noreg
    renamable $lr = t2LoopDec killed renamable $lr, 1
    renamable $r4, dead $cpsr = nsw tMUL killed renamable $r5, killed renamable $r4, 14, $noreg
    renamable $r5, dead $cpsr = tADDrr renamable $r0, renamable $r2, 14, $noreg
    $r10, $r8 = t2LDRDi8 $r5, 4, 14, $noreg
    renamable $r9 = t2LDRi12 renamable $r5, 12, 14, $noreg
    tSTRr killed renamable $r4, renamable $r0, $r2, 14, $noreg
    renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r2, 14, $noreg
    renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 16, 14, $noreg
    renamable $r6 = tLDRi renamable $r4, 1, 14, $noreg
    renamable $r6 = nsw t2MUL killed renamable $r10, killed renamable $r6, 14, $noreg
    tSTRi killed renamable $r6, renamable $r5, 1, 14, $noreg
    renamable $r6 = tLDRi renamable $r4, 2, 14, $noreg
    renamable $r6 = nsw t2MUL killed renamable $r8, killed renamable $r6, 14, $noreg
    tSTRi killed renamable $r6, renamable $r5, 2, 14, $noreg
    renamable $r4 = tLDRi killed renamable $r4, 3, 14, $noreg
    renamable $r4 = nsw t2MUL killed renamable $r9, killed renamable $r4, 14, $noreg
    tSTRi killed renamable $r4, killed renamable $r5, 3, 14, $noreg
    t2LoopEnd renamable $lr, %bb.8, implicit-def dead $cpsr
    tB %bb.9, 14, $noreg

  bb.9 (%ir-block.49):
    successors: %bb.4(0x40000000), %bb.10(0x40000000)
    liveins: $r0, $r1, $r3, $r12

    t2CMPri killed renamable $r12, 0, 14, $noreg, implicit-def $cpsr
    tBcc %bb.4, 0, killed $cpsr

  bb.10 (%ir-block.52):
    liveins: $r0, $r1, $r3

    renamable $r12 = t2LDRs renamable $r1, renamable $r3, 2, 14, $noreg
    renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14, $noreg
    renamable $r12 = nsw t2MUL killed renamable $r2, killed renamable $r12, 14, $noreg
    renamable $r2, dead $cpsr = tADDi3 renamable $r3, 1, 14, $noreg
    renamable $lr = t2LDRs renamable $r0, renamable $r2, 2, 14, $noreg
    t2STRs killed renamable $r12, renamable $r0, killed renamable $r3, 2, 14, $noreg
    renamable $r1 = t2LDRs killed renamable $r1, renamable $r2, 2, 14, $noreg
    renamable $r1 = nsw t2MUL killed renamable $lr, killed renamable $r1, 14, $noreg
    t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r2, 2, 14, $noreg
    $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r8, def $r9, def $r10
    tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc

...
